Memory Layout Engineer

Permanent
Bangalore
Posted 5 years ago

Job Description

Memory leaf cell layout development
Migration of layout from one tech node to another
Block and top level integration
Quality and timely delivery
EM-IR, area intensive layouts, Quality checks (QC)
Understanding of design rules for 90nm and below
Drive multiple projects and provide necessary technical guidance to the engineers
Work Experience Requirements:
Understanding of DFM and DFY
Understanding of memory compiler architectures
Good debugging skills
Knowledge of scripting in PERL/Shell/TCL scripting etc
Proficient with tools like Cadence Virtuoso, Calibre LVS and Calibre DRC

Job Features

Job CategoryLayout Engineer
Exp2 - 7 Yrs

Apply Online

A valid email address is required.
A valid phone number is required.